Founded in 2019 with the support of the European Union 🇪🇺, SiPearl embodies Europe's dream of mastering the technological heart of its supercomputers: the microprocessor.
SiPearl is building Rhea, the high-performance, low-power European microprocessor dedicated to supercomputing and AI inference.
This new generation of microprocessors will first target EuroHPC Joint Undertaking ecosystem, which is deploying world-class supercomputing infrastructures in Europe for solving major challenges in medical research, artificial intelligence, security, energy management and climate with a reduced carbon footprint.
SiPearl is working in close collaboration with its 30 partners from the European Processor Initiative (EPI) consortium - leading names from the scientific community, supercomputing centers and industry - which are its stakeholders, future clients and end-users.
SiPearl employs more than 190 people in:
SiPearl is part of French Tech Next 120 programme 2024 class.
The SiPearl Hardware R&D needs to extend his skillset in RTL verification.
Working under the CAD/flow team manager direction, the candidate will work on the methodologies and the developments of tools for RTL design and verification. The candidate will work closely with the engineering, and propose methodologies and tools the verification, for a better efficiency and coverage.
* Assessement and enhancement of the verification methodology on a large-scale project
* work with engineering to understand the current implementation
* work with EDA vendor to ensure the best usage of the EDA tools
* drive the methodology improvements for verification
* propose and develop flow tools around verification for a better execution
* Support
* support on verification implementation
* support on execution
* Monitoring
* define the metrics to monitor the verification coverage
* define the metrics of execution
* work on data collection and exploitation
* a prior experience of verification or design of complex SoC
* a prior experience with workflow definition and support
* experience with SytemVerilog/UVM/SystemC/C++, EmbeddedC
* experience with git and Gitlab
* knowledge of scripting languages like Bash/Perl/Python
* a willingness to work with users to understand their needs, support them, and provide them with better solutions
* knowledge of FPGA or emulators simulations is a plus
* knowledge of incremental build systems is a plus
Dear candidate, even if you consider you do not fulfill all the qualifications mentioned above, please still apply and share with us why you believe you would be a good fit.
✔️Discovery interview with our Talent Acquisition Partner (30 min)
✔️ AssessFirst personality test - no need to worry, there is no wrong or right answer; our goal is to see beyond your resume (45')
✔️ 2 Technical interviews (1h each)
✔️ Interview with one HRBP in order to answer to your last questions (30 min)
Are you curious to learn more about us?
At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company's goals and values.
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